As the integrity of semiconductor memory device is increased, cell dimension and distance between cells are decreased. In the meantime, it is required a capacitor to have great capacitance, since the capacitor should maintain certain degree of capacitance.
In this regard, to optimize the capacitance of a capacitor, a high dielectric layer such as a (barium/strontium)titanium oxide {(Ba,Sr)TiO.sub.3 ;BST} layer having high dielectric constant has been used as a capacitor insulating layer. When such high dielectric layer is applied to for the capacitor insulating layer, a metal layer of Platinum(Pt) is used as an electrode for the capacitor.
FIG. 1 is a cross-sectional view showing a method for fabricating a semiconductor memory device having a high dielectric layer as a capacitor insulating layer.
Referring to FIG. 1, an intermetal insulating layer 11 is formed on a semiconductor substrate 10 provided with a junction region 10a. Then, the intermetal insulating layer 11 is etched to expose thereby forming a contact hole H. A contact plug 12 is formed of an impurity-doped polysilicon layer within the contact hole H according to a known method. A barrier metal layer 13 comprised of a titanium 13a and a titanium nitride 13b, is deposited on the contact plug 12 and the intermetal insulating layer 11. A Pt metal layer for lower electrode is deposited on the intermetal insulating layer 11 in which the barrier layer 13 is formed. The Pt metal layer for lower electrode and the barrier layer 13 are patterned to be remained on and around the contact plug 12 thereby forming a lower electrode 14. A high dielectric layer 15, for example a BST layer is formed on the intermetal insulating layer 11 in which the lower electrode 14 is formed. A Pt metal layer for upper electrode is formed on the high dielectric layer 15, and then is patterned thereby forming an upper electrode 16. At this time, by taking into consideration that the Pt metal layer for upper electrode has fine cell dimension and distance, the Pt layer for upper electrode is formed according to the chemical vapor deposition(CVD) method incurring excellent step coverage. When the Pt layer is deposited according to the CVD method, a Pt precursor is required. As for such precursor, organic metal materials such as Pt(C.sub.5 H.sub.7 O.sub.2).sub.2, (C.sub.5 H.sub.5)Pt(CH.sub.3).sub.3, (CH.sub.3 C.sub.5 H.sub.4)Pt(CH.sub.3).sub.3 and Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 can be used. However, when Pt(C.sub.5 H.sub.7 O.sub.2).sub.2 is deposited, high temperature of over 500.degree. C. is required and the depositing rate is very slow. Furthermore, since the stability of (C.sub.5 H.sub.5)Pt(CH.sub.3).sub.3 and (CH.sub.3 C.sub.5 H.sub.4)Pt(CH.sub.3).sub.3 is very low, they are applied to real production rarely. On the other hand, Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 is deposited at temperature below 500.degree. C. and has excellent thermal stability. Especially, since the precursor of Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 includes F atom or element, the F atom is trapped on a dangling bond of an interface between the high dielectric layer and the Pt layer for upper electrode during depositing Pt layer for upper electrode. Thus, leakage current is decreased by the elimination of trap sites.
This results can be proved by following graphs.
First, FIG. 2 is a graph showing voltage vs. dielectric constant of the high dielectric layer. The curve (A) in FIG. 2 is a result when the Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 is used as a precursor and a top Pt layer is formed according to the CVD method. The curve (B) is a result when the MeCpPt(Me).sub.3 is used as a precursor and a top Pt layer is formed according to the CVD method. And, the curve (C) is a result when the top Pt layer is deposited according to the physical vapor deposition(PVD) method. According to FIG. 2, the curve (A) has relatively higher dielectric constant than the curves (B) and (C) at the same voltage. This is because the Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 is used as a precursor. Then, trap sites reduce at the interface between the high dielectric layer 15 and the upper electrode 16 thereby lowering leakage current. By the stable interface characteristics, the thickness of interfacial layer is reduced thereby improving dielectric characteristic of the high dielectric layer 15.
FIG. 3 is a graph showing the Auger-Electron Spectroscopy(AES) when the Pt layer is used as the Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 precursor. Referring to FIG. 3, there are a multitude % of F at the interface between the top Pt layer for upper electrode and the high dielectric layer. That means, the F bond is trapped on a dangling bond existing on the interface between the Pt layer for upper electrode and the high dielectric layer, thereby obtaining more stabilized leakage current characteristic.
As described, when the upper electrode of the ferroelectric capacitor is formed according to the CVD method using Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 precursor, electric characteristic of the capacitor is improved. However, Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 precursor is expensive material ($300/1 g) that is too expensive to apply mass-production. While Me(CpPt(Me).sub.3 (Pt-10) is cheaper than Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 precursor, however electric characteristic of capacitor, e.g. dielectric property of dielectric layer and leakage current characteristic, is inferior to Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2.